1. Field of Invention
The present invention relates to a method for manufacturing integrated circuits. More particularly, the present invention relates to a method for forming a dynamic random access memory (DRAM) capacitor that utilizes a liquid-phase deposition method for selectively depositing silicon dioxide onto the required layer.
2. Description of Related Art
As the microprocessor of a computer becomes more powerful, the amount of software programs that can be run inside a computer simultaneously increases exponentially. Consequently, the amount of memory space necessary for storing data must also be increased, and highly efficient memory capacitors are in great demand. As the level of integration of DRAMs increases, DRAM cells are now constructed from just one transfer field effect transistor and a storage capacitor. FIG. 1 is an equivalent circuit diagram of a DRAM cell. A DRAM is normally constructed from an array of these cells. A binary bit is stored in the capacitor C of each cell. In general, when the capacitor C is uncharged, a logic state of "0" is defined. On the other hand, when the capacitor C is fully charged, a logic state of "1" is defined. A capacitor C has an upper electrode (cell electrode) 100 and a lower electrode (storage electrode) 102 with a layer of dielectric 101 sandwiched between the two to provide the necessary dielectric constant. In addition, the capacitor C is coupled to a bit line (BL), and reading and writing to and from the DRAM memory is achieved by charging or discharging the capacitor C. Charging and discharging of the capacitor is carried out through the control of a transfer field effect transistor T (TFET). The source terminal of the transfer transistor is connected to the bit line BL while the drain terminal of the transfer transistor is connected to the capacitor C. The transfer transistor is switched on or off through a selection signal coming from a word line WL, which is connected to the gate terminal of the transfer transistor. Hence, whether the capacitor C is connected to the bit line allowing for charging or discharging of the capacitor depends upon the selection signal passed to the gate terminal.
A conventional DRAM having storage capacity smaller than one megabit (Mbits) has two-dimensional capacitors, commonly referred to as a planar type of capacitor. However, a planar type capacitor occupies lots of substrate area, and so is unsuitable for high level integration. Highly integrated DRAM circuits, for example, those with memory having a storage capacity larger than about four Mbits, need three-dimensional capacitors. Three-dimensional capacitor constructs include the stacked type and the trench type.
Compared with a planar type of capacitor, a stacked type or a trench type of capacitor is able to provide the same capacitance to a capacitor despite a dimensional reduction. However, when the scale of integration for memory devices is further increased, for example, DRAM memory that can store up to 64 Mbits, even a simple three-dimensional capacitor construct is not enough.
One method of further increasing the surface area of the lower electrode, hence increasing the capacitance of a capacitor, is to develop horizontal extensions and then stacking them one over the other as in a fin-type of stacked capacitor. Description of this type of design appears in an article by Ema et al. with the title "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs", published in International Electron Devices Meeting, pp 592-595, December 1988, or U.S. Pat. No. 5,071,783, U.S. Pat. No. 5,126,810 and U.S. Pat. No. 5,206,787.
Another method is to allow the electrode and the dielectric film of the capacitor to extend vertically up to form a vertical structure called a cylindrical stacked capacitor. Description of this type of design appears in an article by Wakamiya et al. with the title "Novel Stacked Capacitor Cell for 64 Mb DRAM", published in Symposium on VLSI Technology Digest of Technical Papers, pp 69-70, 1989, or U.S. Pat. No. 5,077,688.
Yet, in the near future, the trend for integrating more and more devices into a wafer will continue, and the dimensions of a DRAM cell will shrink still further. As anybody familiar with the technologies may understand, shrinking of memory cell dimensions will lead to a further reduction of the capacitance for its capacitor. One consequence of this is the production of more soft errors due to an increased effect by alpha rays. Therefore, people engaged in the semiconductor industry are still searching for ways to increase the capacitance of a capacitor even though the available area is reduced.
In light of the foregoing, there is a need provide an improved method of fabricating a DRAM capacitor.